The present invention relates to the selective modification of the drive strength of a finFET (Fin Field Effect Transistor). In particular the invention provides methods for forming finFETs with a selectively modified drive strength and to circuits resulting from the application of those methods to the fabrication of integrated circuits. The present invention is particularly suited to, but not limited to, use in a Static Random Access Memory (SRAM) cell.
CMOS (Complementary Metal Oxide Semi-conductor) technology is widely used today in integrated circuits used in, for example, microprocessors, microcontrollers, memory circuits and other digital logic circuits, as well as in a wide variety of analog circuits. CMOS technology relies on MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) to amplify or to switch signals.
It is desirable to be able to differentiate the drive strengths of transistors within a CMOS circuit. For example one area in which it has been found to be advantageous to differentiate the drive strengths of transistors is within a Static Random Access Memory (SRAM) cell. A typical SRAM cell circuit with 6 transistors (6-T SRAM cell) is shown in FIG. 1, and a typical implementation of such a cell in conventional planar CMOS technology is shown in FIG. 2.
The exemplary 6-T SRAM cell shown in FIG. 1 comprises first and second cross-coupled inverters 2, 4 each inverter 2, 4 comprising a respective P-MOS Pull-Up (PU) transistor 6,8 and a N-MOS Pull-down (PD) transistor 10,12 coupled in series between the power source Vdd and ground Gnd. A first respective N-MOS Pass-gate (PG) transistor 14 is coupled between a bit-line 16 and an internal node 18 connecting the first pull-up transistor 6 and the first pull-down transistor 10. A second respective N-MOS pass-gate transistor 20 is coupled between an inverted bit-line 22 and an internal node 24 connecting the second pull-up transistor 8 and the second pull-down transistor 12. As will be apparent to a skilled person, corresponding inverted values are held by the internal nodes 18, 24.
The exemplary 6-T SRAM cell stores one bit and has two stable states, in which either internal node 18 or internal node 24 are asserted, which are used to denote a 1 or 0 for the bit. Access to the exemplary 6-T SRAM cell during both a read operation and a write operation is enabled by the word line WL, which turns on the first and second pass-gate transistors 14, 20 thus coupling the internal nodes 18, 24 to the bit lines 16, 22 respectively. For example, during a read operation, the bit lines 16 and 22 are both pre-charged to logic 1, before asserting the word line WL to turn on first and second pass-gate transistors 14, 20. Thereafter, the bit line corresponding to whichever of the internal node 18 or 24 started at logic 0 will discharge into the cell via the respective pass-gate transistor 14, 20 and the respective pull-down transistor 10,12. A detailed discussion of the read and write operation of a 6-T SRAM cell will be omitted since a skilled person will be familiar with the layout and operation of 6-T SRAM cell.
As is well known, the performance of a SRAM cell is dependent on the relative drive strengths of the transistors making up the SRAM cell. In this context, the term drive strength of a transistor is intended to mean the magnitude of the current flowing through the transistor when the transistor is switched on.
Conventionally designers of SRAM cells have been able to adjust all the major performance metrics of a SRAM cell, such as access time, static noise margin and write margin, by adjusting the transistor widths and lengths in planar CMOS technology to control the drive strengths of the respective transistors. Thus, for example in a SRAM cell implemented in conventional planar bulk CMOS technology the source and drain regions of the pull-down transistor can be made wider than the source and drain regions of the corresponding pass-gate transistor, thus increasing the drive strength of the pull-down transistor relative to the drive strength of the pass-gate transistor. The read time of the cell can therefore be improved.
A typical implementation of the SRAM cell of FIG. 1 in conventional planar CMOS technology showing the differentiation of the transistor dimensions is shown in FIG. 2. In FIG. 2 the same reference numerals as the reference numerals for the corresponding features in FIG. 1 have been used. In addition, interconnection 26 interconnects the gate of pull-up transistor 8; the gate of pull-down transistor 12; the drain of pull-up transistor 6; the drain of pull-down transistor 10 and the internal node side of the pass-gate transistor 14, and thus represents the internal node 18. An interconnection 28 interconnects the gate of pull-up transistor 6; the gate of pull-down transistor 10; the source of the pull-up transistor 8; the drain of pull-down transistor 12 and the internal node side of pass-gate transistor 20, and thus represents the internal node 24. As can be seen, the widths of the pull-down transistors 10, 12 are greater than the widths of the corresponding pass-gate transistors 14, 20, giving the pull-down transistors 10, 12 greater drive strength and thus improving the performance of the SRAM cell. It is noted that the pull-up transistors 6, 8 are P-MOS transistors, while the other transistors are N-MOS transistors.
However, due to increasing variability, it is becoming increasingly difficult to manufacture a SRAM array of several Mbits in planar CMOS technology with an acceptable yield as the density of the integrated circuits is increased. In addition, as the size of the individual MOSFETS is reduced, the performance of the MOSFETS degrades, in particular due to so-called short channel effects.
At the present it is expected that conventional planar MOSFETs will reach the limit of miniaturisation by 2010, concurrent with the widespread adoption of 32 nm technologies.
FinFETs have been suggested as potential replacements for conventional planar MOSFETS. The distinguishing characteristic of the finFET is that the conducting channel is wrapped around a thin silicon “fin” which forms the body of the device. One or more gate electrodes are formed adjacent the fin. In a dual-gate device, one gate electrode on each side of the fin is formed. In a tri-ate device, one gate electrode on each side of the fin and one gate electrode at the top of the fin are formed. These arrangements enable good gate control over the channel, resulting in improved short channel immunity and improved ratio between the channel current when the transistor is switched on and the channel current when the transistor is switched off. The structure of a typical finFET will be described with reference to FIGS. 3-5.
FIG. 3 is a plan view of a typical finFET structure. FIG. 4 is a longitudinal cross-section through the line A-A in FIG. 1. FIG. 5 is a perspective view of a typical finFET structure showing the fin and the gate structures. In FIG. 5 the drain region and the source region of the finFET have been omitted for clarity.
The finFET 30 is provided with a narrow and relatively high fin 32 upstanding from the surface of the substrate 34 (seen best in FIGS. 4 and 5). The fin 32 is typically formed from Silicon on a buried Oxide (BOX) layer of a Silicon (SOI) substrate 34 or on a silicon substrate and has a width Wfin and a Height Hfin. One or more gate electrodes 36 having a gate length Lgate are disposed over the top and sides of the fin 32 and spaced apart from the fin 32 by a spacer 38. Typical dimensions for the fin 32 and gate electrodes 36 for the 32 nm CMOS node would be Lgate=20-50 nm; Wfin=5-20 nm; Hfin=20-100 nm. Adjacent each end of the fin 32 are formed two high density doped (HDD) regions forming a source HDD region 40 and a drain HDD region 42 of the finFET 30. In addition, typically, low density doped (LDD) extension regions, forming source LDD extension region 44 and drain LDD extension region 46, are formed within the channel extending from the source HDD region 40 and drain HDD region 42 respectively towards the gate electrode(s) 36.
It is known to omit the drain LDD extension region of a finFET in order to reduce Gate Induced Drain leakage (GIDL) current within the channel of a finFET, as for example discussed in the article “GIDL (Gate-Induced Drain Leakage) and Parasitic Schottky barrier Leakage Elimination in aggressively scaled HfO2/TiN FinFET devices” Hoffmann et al, Electron Devices Meeting, 2005 IEDM Technical Digest. IEEE International Dec. 5, 2005, Piscataway, N.J., USA.
Many of the performance metrics of a finFET, for example the drive strength of the finFET, are determined by the effective channel width of a finFET which in turn depends upon the dimensions of the fin. In particular, the effective channel width of a finFET is given by 2×Hfin (for a dual gate FinFET) and 2×Hfin+Wfin (for a tri-gate finFET). The person skilled in the art will be familiar with the principles of operation of a Field Effect Transistor (FET) and therefore a detailed description of the operation of the finFET will be omitted.
An exemplary implementation of the SRAM cell of FIG. 1 using finFETs is shown in FIG. 6. In FIG. 6 reference numerals corresponding to reference numerals used in FIG. 2 are used for the corresponding features. As can be seen from a consideration of FIG. 6, in this exemplary silicon layout implementation, the finFET pass-gate transistor 114 shares a common fin with the finFET pull-down transistor 110 and the finFET pass-gate transistor 120 shares a common fin with the finFET pull-down transistor 112. As a result, the drive strengths of the transistors in the SRAM cell implementation shown in FIG. 6, in particular the pass-gate transistors 114,120 and the pull-down transistors 110,112 cannot easily be altered independently.
Previously several different methods have been suggested to increase the drive strength of a finFET. In a first method disclosed for example in U.S. Pat. No. 6,706,571 an additional fin parallel to the fin common with the pass-gate transistor is provided for each pull-down transistor in a SRAM cell. However, the addition of the extra fin results in an undesirable increase in area used by the SRAM cell. In a second method disclosed for example in H. Kawasaki et al “Embedded Bulk FinFET SRAM cell Technology with planar FET peripheral circuit for hp 32 nm node and beyond”, Symposium on VLSI Technology digest of Technical papers, 2006, the fin height of adjacent finFETs in a cell built on bulk Si is adjusted to alter the drive strength of the finFETs. However, it is difficult to apply this technique to the mass fabrication of integrated circuits and especially difficult to apply this technique to finFETs built on a SOI substrate. In a third method proposed in Z. Guo et al., “FinFET-based SRAM Design”, Proceedings of the 2005 International Symposium on Low Power Electronics and Design (ISPLED'05), pp 2-7, 2005, the pull-down transistors are rotated by 45 degrees so that the channels are formed in the [100] plane, resulting in an improvement in the Signal Noise Margin (SNM) owing to the improved electron mobility in the [100] plane compared with the conventional [110]. However, again this technique is complex and it is difficult to apply this technique to the mass fabrication of integrated circuits.
The present inventors have realised it would be desirable to be able to selectively modify the drive strength of a finFET in a CMOS circuit or to differentiate the drive strengths of two or more finFETs in a CMOS circuit.